This application relates to test system clocks used to generate test patterns and clock signals for test circuits, such as integrated circuit devices.
Test systems for testing high-speed integrated-circuit devices (i.e., device under test (DUT)), such as microprocessors, have become increasingly sophisticated due to the need for generating precise clock signals and test pattern signals. The clock signals are provided to a DUT's clock input pin and used to run the DUT, while the test pattern signals are used to drive and strobe the DUT's data pins.
Test pattern signals (which are also referred to as “event sequences”) generally include a pattern of events, such as binary values (1s and 0s), and an associated time for the occurrence of each event at its rising and falling edges, which is usually referred to as a test period. Events usually are one of two event types—drive events that drive a DUT data pin to a particular state, and strobe events (also called test events) that test the state of a DUT data pin. FIG. 1 illustrates an example of a test pattern 100, such as may be generated for testing a DUT. In this example, the test pattern 100 includes four events. An event is a pair (S,T) where “S” is a state and “T” is the time associated with the transition to the state. For example, test pattern 100 has four drive events which can be written as (D1,1), (D0,8), (D1,13) and (D0,18). The first event is driving the signal to a high state (1) at time equal to 1. The second event is driving the signal to a low state (0) at time 8. The third event is driving to a high state (1) at time 13. The fourth event is driving to a low state (0) at time 18. The test period of the test pattern 100 is the time between time 1 and time 13, which is repeated for successive generations of the drive events.
In developing a test pattern signal, a test system needs a mechanism for generating a pattern of events in which rising and falling edges can be placed at precise times within a chosen test period with reference to the test system's master clock. Assuming the master clock has a period of 2.5 nanoseconds (ns), the test system should be able to place rising/falling edges with a precision on an order of 10 picoseconds (ps). As shown in FIG. 2, generating a test pattern signal with a test period that is a multiple of the master clock 200's period (e.g., 2.5 ns or 5.0 ns) can be done by using a programmable divider 204. Generating a test pattern signal having a test period that is between a multiple of the master clock period (e.g., 2.7 ns or 5.5 ns) can be done by using a vernier technique, which is implemented by a vernier circuit 210, to provide a programmable period off-set 212 (which is referred to as a “period vernier”) to the master clock 200's period or multiple of the master clock 200's period. Generally, the period vernier 212 value is used to adjust the master clock period to achieve a desired test period 216 suitable for a particular test pattern signal. Test systems, such as those described in U.S. Pat. Nos. 6,128,754, 5,673,275 and 5,212,443, the disclosures of which are incorporated by reference, describe the use of a vernier technique to generate a period vernier.
Because the vernier technique is a digital approach to frequency synthesis, it generally has certain advantages, such as increased flexibility (i.e., the ability to easily place events in the test periods) and the ability to change period instantaneously during run-time. However, the vernier circuit is inherently analog in nature, and, therefore nonlinear. The vernier circuit's nonlinearity tends to have a large effect on the edge placement accuracy (EPA) of the test period and the period-to-period jitter of the test period. Typically values of the period-to-period jitter can be 20 ps. On a spectrum analyzer, jitter typically shows up as spurs spaced by the frequency at which the vernier-based clock cycles.
A clock signal that is used to run the DUT generally needs to be phase synchronized with and frequency similar to the test pattern signal. Frequency similar means the clock signal is a multiple of a sub-multiple of the test pattern signal. Generally, a vernier-based clock is used to generate the clock signal for the DUT.